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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:37:09 01/15/2011 
-- Design Name: 
-- Module Name:    config_counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use WORK.constants.all;

entity Config_Counter is
	port(
		clk				: in std_logic;
		reset			: in std_logic;
		soft_rst    : in std_logic;
		load			: in std_logic;
		seed			: in std_logic_vector(DATA_SIZE-1 downto 0);
		end_of_count	: out std_logic
	);
end Config_Counter;

architecture BEHAVIORAL of Config_Counter is
begin
	-- purpose : Takes the value in input and transfort into an unsigned integer.
    --           Starts decrementing the this when the load signal goes to 0.
	--           Once the null value is reached, the signals end_of_count goes to 0
	P_counter : process(clk, reset, load)
		variable temp_logic	: std_logic_vector(DATA_SIZE-1 downto 0) := (others => '0');
		variable temp_int	: integer;
	begin
		if reset = '1' then
			temp_logic		:= (others => '0');
			temp_int		:= 0;
			end_of_count	<= '1';
		elsif soft_rst = '1' then 
			
		elsif ( clk'event and clk = '0' ) then
			if load='1' then
				temp_logic	:= seed;
				temp_int	:= conv_integer(unsigned(seed));
			else
				if ( temp_int > 0 ) then
					temp_int	:= temp_int - 1;
					temp_logic	:= conv_std_logic_vector(temp_int, DATA_SIZE); -- convert  int to std_logic
					
					-- generation of the end of count output
					if ( temp_logic = X"00000000" ) then
						end_of_count <= '0';
					end if;
				else
					end_of_count <= '1';
				end if;
			end if;
		end if;
	end process;
end;

